PolyU EIE4110 VLSI

  EIE Lab 4 Laboratory   Objectives The   objectives   of   this laboratory   are: ·          Understand   the   use   of Altera’s MegaWizard   IP   generator: ( https://ftp.intel.com/Public/Pub/fpgaup/pub/Teaching_Materials/current/Tutorials/Verilog/Using_Library_Modules.pdf ) ·          How   to specify   synthesis   options   and   their   impact ·          Understand   the   impact   of   placement   on   the   design   quality   using  Pin  Planner Project files are archieved in Google drive:  https://drive.google.com/drive/folders/1HCdlSi3-0b2UOdJ-86M2q64Z-IPnD7PN?usp=sharing Top entry sqrt.v file: // ----- EIE Lab 4 // -----     https://vlsiorfpgadesign.blogspot.com/     ----- // // Using I...

   EIE EIE4110 Lab #3 This article is to present a Verilog code for Sequence Detector using Moore FSM. A Verilog Testbench for the Moore FSM sequence detector is also provided for simulation below.  The Moore FSM keeps detecting a binary sequence from a digital input and the output of the FSM goes high only when a "1011" sequence is detected. For a state diagram of the Moore FSM for the sequence detector, you might refer to the website at this hyperlink:  https://www.fpga4student.com/2017/09/verilog-code-for-moore-fsm-sequence-detector.html You can also find some similar verilog files of the lab are placed in the Google Drive (hyperlink below), for reference: (you can just download the Quartus files) https://drive.google.com/drive/folders/1ARnWCZSUym3DMnA0rp0RT7bdNTfso2CN?usp=sharing Design Architecture: State Diagram (Click the picture to enlarge) Verilog code is designed as an example as follows: // -----     https://vlsiorfpgadesign.blogspot.com/...

Intel (Altera) Terasic DE1-SoC Development Board (Cyclone V)    Video:  https://youtu.be/sKhvMhTiuM4 For the development board of Terasic development board DE1-SoC using Inter's (Altera) Cyclone V (28nm SoC 5CSEMA5F31C6N),  With ARM Cotex-A9 main processor, below are some tutorials for your references:  Tutorial 1a: Get started with Altera FPGA SoC and Linux Yocto on Terasic DE1-SoC dev board   Objectives: To learn how to configure HPS, add it into your FPGA project and establish communication between HPS and FPGA.  Procedures:  1) Create a new project and select your device (Cyclone V, 5CSEMA5F31)  2) Import the pin assignment  3) Open Qsyst and add HPS, other peripherals  4) Configure HPS  5) Add HPS components into your FPGA design - Dont forget to execute the TCL files  6) Create HPS header file by executing the "generate" file  7) Write your program and compile it using a makefile  8) Assign IP address ...