VLSI VHDL Design Labs (2017-2019 VHDL versions)
Lab 7 - Labs using VHDL - VGA Timing Control Laboratory Objectives The objectives of this laboratory are: · Create a VGA interface interfacing the FPGA with a monitor · Prototype the design on the Terasic DE1-SoC FPGA board · Understand the timing reports before and after place and route FPGA Design The following is to draw a blue square over a yellow background on the monitor as shown in the picture below The VGA controller should generate the entire control signa...