VLSI VHDL Design Labs (2017-2019 VHDL versions)

  Lab 7 - Labs using VHDL - VGA Timing Control

Laboratory Objectives

The objectives of this laboratory are:

·        Create a VGA interface interfacing the FPGA with a monitor

·        Prototype the design on the Terasic DE1-SoC FPGA board

·        Understand the timing reports before and after place and route

FPGA Design

The following is to draw a blue square over a yellow background on the monitor as shown in the picture below

The VGA controller should generate the entire control signal to drive the VGA output of the development board. The  controller should have the following architecture:

Figure 1 Typical Block Diagram of VGA Controller (Click to enlarge)

Reference: http://eewiki.net/pages/viewpage.action?pageId=15925278

Background

VGA is a standard interface for controlling the analog monitors. The computing side of the interface provides the monitor with horizontal and vertical sync signals, color magnitudes, and ground references. The horizontal and vertical sync signals are 0V/5V digital waveforms that synchronize the signal timing with the monitor. To be controlled by digital logics, they are provided directly by the FPGA (3.3V can meet the minimum threshold for a logical high level, so 3.3V can be used instead of 5V).

 

The color magnitudes are 0V-0.7V analog signals sent over the R, G, and B wires.(Alternatively, the green wire can use 0.3V-1V signals that incorporate both the horizontal and vertical sync signals, eliminating the need for those lines. This is called sync-on-green and is not addressed here.) The three color magnitude wires are terminated with 75Ω resistors. These lines are also terminated with 75Ω inside the monitor. To create these analog signals, the FPGA outputs an 8- bit bus for each color to a video DAC, in this example an ADV71235 from Analog Devices (data sheet attached). This video DAC also requires a pixel clock to latch in these values.

The VGA interface also specifies four wires that can be used to communicate with a ROM in the monitor. This ROM contains EDID (extended display identification data), which consists of the monitor’s parameters in a standard format. Several communication standards exist to access this data, but in the simplest case, these lines can be left unconnected.

Connections

 

Figure 2 Standard VGA Connector

Table 1 VGA connections description